Very large scale integrated ("VLSI") circuits often contain digital and analog portions. The digital portions may include both low-voltage circuitry where the supply voltage typically is 3.3-5 V and high-voltage circuitry where, as with the analog portions, the supply voltage is greater than 5 V, typically 15 V or more. Field-effect transistors, specifically these of the MOS type, constitute the main active circuit elements currently used in VLSI circuits. The characteristics of FETs in the analog and high-voltage digital portions typically differ from the characteristics of FETs in the low-voltage digital portions.
MOS transistors used in the low-voltage digital circuitry of a VLSI circuit are typically manufactured at the minimum gate length that can be reliably formed (e.g., photolithographically printed) and still yield acceptable electrical performance characteristics. Device miniaturization has brought the minimum gate length down to 0.25-1.0 .mu.m. As the minimum gate length is reduced, physical parameters such as gate dielectric thickness, source/drain junction depth, net channel doping, threshold voltage, and supply voltage are adjusted together according to appropriate scaling rules. This enables MOS transistors to be fabricated at small dimensions without the deleterious effects, such as non-saturating output characteristics, threshold-voltage dependence on channel length, and drain-induced current leakage, that are associated with short-channel FETs.
The gate dielectric thickness and source/drain junction depth usually scale in an approximately proportional manner with the gate length. The channel doping scales inversely with the gate length. However, the threshold voltage varies with the gate length in a more complicated manner. In fact, the threshold voltage is sometimes described as not scaling with the gate length.
Various techniques have been employed in the prior art to address the non-scalability of the threshold voltage. One of the techniques is to perform a global (blanket) ion implantation into the channel of an FET so as to independently adjust its threshold voltage. FIGS. 1 and 2 are helpful in understanding the effect of a global threshold-adjust implant.
FIG. 1 illustrates a conventional n-channel MOS transistor 10 in which a threshold-adjust implant is not used. FET 10 is created from p-monocrystalline silicon ("monosilicon") substrate 11 having p well 12. Channel zone 13 separates n++ source 14 and n++ drain 15. Gate dielectric layer 16, typically silicon oxide, electrically insulates n++ polycrystalline silicon ("polysilicon") gate electrode 17 from channel 13. The gate length and thus also the channel length, which is slightly less than the gate length, are measured horizontally in the plane of FIG. 1. Items 18 and 19 respectively indicate the well-side boundaries of the source-well and drain-well depletion regions when the gate-to-source voltage, commonly referred to as the gate bias, is zero, and the drain-to-source voltage is at a positive (e.g., 5-V) operating value.
As the gate length is reduced, all the other transistor parameters being the same in FET 10, the source-well depletion region approaches the drain-well depletion region. If the gate length is reduced to such a value that the source-well depletion region meets the drain-well depletion region, the operative length of channel 13 is reduced to zero even though the metallurgical (source-junction-to-drain-junction) channel length is greater than zero. Source 14 punches through to drain 15, enabling current to flow from source 14 to drain 15 with zero gate bias. The drain current increases in a rapid, undesirable manner with increasing drain voltage. FET 10 is disabled as an amplifying or switching device.
FIG. 2 depicts an n-channel MOS transistor 20 configured generally the same as FET 10 except that a light dosage of p-type dopant is globally provided in channel 13 to adjust the FET threshold voltage. Because the threshold-adjust dopant is of the same conductivity type (p-type) as well 12, the threshold voltage is increased. The threshold adjustment is typically performed by ion implanting boron (or a boron-containing species) through the upper silicon surface in a blanket manner--i.e., without using an implant mask--and later performing an anneal to activate the implanted boron. Item 21 generally indicates the location of the threshold-adjust dopant. The resulting vertical dopant concentration profile through the center of FET 20 is shown in FIG. 3.
Use of a threshold-adjust implant permits the threshold voltage to be controlled independently of the doping in well 12 and substrate 11. Importantly, the well/substrate doping can be reduced so as to reduce the source/drain junction capacitances, thereby enabling FET 20 to switch faster. Although reduced well/substrate doping enables the depletion regions for source 14 and drain 15 to become wider below zones 14 and 15, the increased p-type doping in channel 13 reduces the distance by which the drain-well depletion region extends into channel 13. This reduces the likelihood of source-drain punchthrough. At the same time, the overall structure of the electric field in the vicinity of the drain-well junction is more relaxed. Consequently, the drain-to-well breakdown voltage is increased.
Also, when p well 12 is reverse biased with respect to source 14, the threshold voltage effectively increases due to the so-called "body effect". Specifically, the gate voltage needed to reach channel conduction must be increased to compensate for the additional fixed charge exposed in the channel depletion region below gate electrode 17 as a result of the well-to-source reverse biasing. The threshold-adjust implant reduces the body effect and thus the amount by which the threshold voltage is increased during such operation.
The improvement in the body effect and the ability to independently control the threshold voltage can be seen by first considering the following equations for a simple long-channel MOS transistor of the type generally shown in FIG. 1 except that substrate 11 and well 12 are replaced with a uniformly doped silicon substrate: ##EQU1## EQU .vertline.Q.sub.B .vertline.=qN.sub.B y.sub.dmax (2) ##EQU2## where: V.sub.T is the threshold voltage,
V.sub.FB is the flat-band voltage, PA1 Q.sub.B is the bulk charge density per unit in the surface depletion region (below the gate electrode), PA1 C.sub.ox is the gate-oxide capacitance per unit area, PA1 N.sub.B is the average net dopant concentration per unit volume in the substrate, PA1 y.sub.dmax is the maximum depletion width of the surface depletion region at inversion, PA1 V.sub.B is the substrate bias voltage, PA1 n.sub.i is the intrinsic carrier concentration of silicon, PA1 q is the electronic charge, PA1 K.sub.s is the relative dielectric constant of silicon, PA1 .epsilon..sub.0 is the permittivity of free space, and PA1 T is the absolute temperature.
.phi..sub.Fp is the Fermi potential of the p-type channel material,
At fixed substrate bias voltage V.sub.B and interface properties, maximum depletion width y.sub.dmax is essentially fixed. Oxide-capacitance parameter C.sub.ox is a function of the gate oxide thickness. If the gate oxide thickness is also fixed, threshold voltage V.sub.T is controlled by bulk charge density Q.sub.B and, per Eq. 2, thus by average substrate dopant concentration N.sub.B. Threshold voltage V.sub.T increases as substrate doping N.sub.B increases, and vice versa.
When the threshold-adjust implant is utilized, Eq. 1 is replaced with: ##EQU3## where N.sub.Th is the net dopant concentration per unit area of the threshold-adjust layer. Threshold-adjust dopant concentration N.sub.Th can be used to change threshold voltage V.sub.T, thereby allowing voltage V.sub.T to be adjusted without changing substrate doping N.sub.B. Also, the use of the threshold-adjust implant enables a given V.sub.T value to be obtained at a lower N.sub.B value. According to Eqs. 2-5, this makes voltage V.sub.T less sensitive to substrate bias variations because the additional channel depletion charge caused by substrate bias V.sub.B occurs in a more lightly doped substrate.
Upon considering the FET short-channel effect, Eq. 5 is modified to become: ##EQU4## In Eq. 6, f is a geometrical factor less than one as determined from: ##EQU5## where d.sub.J is the source junction depth, and L.sub.c is the channel length. Eqs. 6 and 7 are provided from the simplified model of Yau, "A Simple Theory to Predict the Threshold Voltage in Short-Channel IGFETs," Solid-State Elecs., 1974, pages 1059-1069. Taking into account the fact that y.sub.dmax varies with the inverse square root of substrate doping N.sub.B according to Eq. 3, Eqs. 6 and 7 together indicate that the V.sub.T reduction which occurs when channel length L.sub.c is of comparable value to source junction depth d.sub.J can be reduced if substrate doping N.sub.B is reduced.
A threshold-adjust implant can be used in virtually all CMOS and BiCMOS fabrication processes where the minimum feature size--i.e., the gate length--is less than 1 .mu.m. As device miniaturization continues, usage of the threshold-adjust implant is expected to continue. It is important that modifications to the structure and fabrication of FETs be developed with a threshold-adjust implant in mind.
While use of a global threshold implant enables the threshold voltage to be adjusted independently of substrate doping N.sub.B, the transistor current drive depends on the channel doping and thus is coupled to the threshold voltage. It would be desirable to weaken this coupling in such a way that the current drive characteristics can be improved without detrimentally affecting the threshold characteristics.
Another important FET design consideration is the breakdown voltage at the drain. The drain-junction breakdown voltage decreases as the background doping increases. Referring to FET 20 in FIG. 2, the doping in p well 12 is, as mentioned above, reduced when a global threshold implant is used. Use of the threshold-adjust implant thus causes the drain breakdown voltage to be improved by relaxing the electric field along the bottom portion of the drain-to-well junction. It would be desirable to further improve the drain breakdown voltage yet still be able to control the threshold voltage independently of substrate doping N.sub.B.
In the device of FIG. 1 or 2, avalanche breakdown at the drain junction occurs near the upper semiconductor surface where the drain junction meets gate oxide 16. This situation, customarily referred to as surface breakdown, impairs device reliability. In particular, when the gate-to-source voltage exceeds the threshold value, some of the charge carriers (electrons) moving towards the drain become sufficiently energetic (hot) in the vicinity of the drain junction along the upper semiconductor surface that they are injected into gate oxide 16 and become trapped there. Gate oxide 16 becomes permanently charged, causing the threshold voltage and FET transconductance to drift with time.
One solution to the hot-carrier problem is to use a lightly doped drain ("LDD") structure for reducing the magnitude of the drain dopant concentration at the upper semiconductor surface where the drain terminates the channel. See Ogura et al, "Design and characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Trans. Elec. Devs., Aug. 1980, pages 1359-1367. Also see Ogura et al, "Elimination of Hot Electron Gate Current by the Lightly Doped Drain-Source Structure," IEDM Tech. Dig., 1981, pages 651-654.
The LDD solution is exemplified by n-channel MOS transistor 30 in FIG. 4. FET 30 is configured similarly to FET 20 except in the vicinity of the source and drain. As indicated in FIG. 4, the drain of FET 30 consists of n++ main portion 31 and more lightly doped n+ extension 32. The source is similarly formed with n++ main portion 33 and more lightly doped n+ extension 34. Dielectric spacers 35 and 36 control the laterally dimensions of n+ extensions 32 and 34. In the conventional example of FIG. 4, FET 30 is provided with a global threshold-adjust implant indicated by p+ layer 21.
At constant gate length, drain extension 32 in FET 30 has a lower doping than drain 15 in FET 20. The electric field at the drain end of the channel is thus lower in FET 30 than in FET 20. As a result, fewer charge carriers in FET 30 become sufficiently energetic to cause a hot-carrier problem. Inasmuch as the LDD technique is widely used in VLSI products, it is desirable that improvements to the structure and fabrication of FETs be compatible with the LDD technique.
Transistors that are fabricated with geometries of minimum-feature size so as to efficiently perform digital signal processing at 5 V or less generally do not interface well with the outside world where voltages considerably above 5 V are commonly encountered. For example, consider the situation when gate electrode 17 of FET 30 is of minimum printable length. Because (a) main drain portion 31 is relatively close to main source portion 33 and (b) gate oxide 16 is relatively thin, subjecting FET 30 to a voltage considerably above 5 V would produce such an intense electric field in the vicinity of main drain portion 31 that FET 30 would breakdown according to a mechanism such as source-to-drain punchthrough.
A manufacturing process used to fabricate low-voltage FETs for a VLSI circuit must invariably also provide differently designed FETs that can perform high-voltage analog or digital functions for interfacing with the outside world. One way of addressing the high-voltage interface problem is to increase the distance between the heavily doped source and drain regions to a value great enough to allow room for the drain electric field to extend into the channel without causing punchthrough breakdown.
FIG. 5 depicts a conventional high-voltage n-channel MOS transistor 40 of the type described in Erb et al, "A High Voltage Ion Implanted MOSFET," IEDM Tech. Dig., 1971, page 158. FET 40 is configured similar to FET 10 except at the drain. The drain of FET 40 is formed with n++ main portion 41 and more lightly doped n+ extension 42. For the same minimum feature size, n+ drain extension 42 in FET 40 is considerably longer than n+ drain extension 32 in FET 30. Also, gate electrode 17 and, consequently, channel 13 are correspondingly longer in FET 40 than in FET 30. Because FET 40 has more room for the electric field to expand in both directions from the drain end of channel 13, FET 40 can tolerate higher drain voltages without having the drain electric field become high enough to cause avalanche breakdown at the drain.
Unfortunately, increasing channel length generally leads to a decrease in current-drive capability. For example, when a device such as FET 40 is performing an analog function at high current, the drain saturation current I.sub.Dsat is given by the classical relationship for strong inversion operation: ##EQU6## where .mu..sub.n is the electron mobility, W is the channel width, V.sub.G is the gate voltage, and V.sub.Dsat is the drain saturation voltage determined from: ##EQU7## As Eq. 8 indicates, increasing channel length L.sub.c causes drain saturation current I.sub.Dsat to decrease. It would be desirable to have a technique for recovering some of the current drive lost when the channel length is increased to a value greater than the minimum manufacturable channel length.
In some analog applications, FETs need to operate at relatively low drain current. Such transistors are usually operated in weak or moderate inversion near the on/off threshold point. Large voltage gains and large voltage output swings can be achieved in weak or moderate inversion because the drain saturation voltage is typically a minimum and the output conductance is essentially zero. Unfortunately, the best performance at weak or moderate inversion has been achieved in the prior art only when the drain current per unit source/drain width is very low. This normally requires that the source and drain be quite wide to achieve a usable level of drain current.
For operation in weak or moderate inversion near the on/off threshold, the transconductance-to-current quotient is a useful parameter of merit. The transconductance-to-current quotient indicates how much transconductance is produced for each unit of output current. It is desirable to increase the drain current per unit source/drain width in weak or moderate inversion without degrading the transconductance-to-current quotient. The drain current can then reach a usable level without exaggeratedly increasing the source/drain width.
Increasing the steepness by which the drain current varies with the gate voltage in the vicinity of the on/off threshold causes an FET to be a better switch. Accordingly, it is desirable to increase the turn-on/turn-off steepness. This is particularly important as VLSI circuits are scaled downward because an FET having a low threshold voltage must turn off abruptly when the gate-to-source voltage drops below the threshold voltage to avoid current leakage at zero gate bias.
FIG. 6 illustrates an approach presented in Armijos, "High-Speed DMOS FET Analog Switches and Switch Arrays," Application Note AN301, Low-Power Discretes, Siliconix, Jun. 22, 1994, pages 33-42, for increasing the breakdown voltage of a discrete high-voltage n-channel FET 50 created from p-monosilicon substrate 51. The drain consists of n+ main drain portion 52 and n-type drain extension 53 which meets channel zone 54 below gate electrode 55. Drain extension 53 is much shallower than main drain portion 54.
A double-diffusion process is utilized in Armijos to create p body region 56 which extends along n+ source 57 and into channel 54. This results in a peaked p-body dopant profile in which the dopant concentration of p body region 56 along the upper semiconductor surface progressively increases and then decreases in going from the right-hand side of source 57 to the right into channel 54 in FIG. 6. Armijos states that body region 56 acts to isolate source 57 from the drain.
Application of the high-voltage discrete FET of FIG. 6 to VLSI circuits such as CMOS or BiCMOS devices is impractical because the use of a LDD extension much shallower than the main drain portion leads to an unacceptably high drain series resistance. Also, the high curvature of drain extension 53 of the drain end of channel 54 results in a drain breakdown voltage that is unacceptably low for VLSI circuits.